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library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity bit1adder is
port(
a,源码bytetcc源码分析b,ci:in std_logic;
s,co:out std_logic
);
end bit1adder;
architecture func of bit1adder is --æ¤åè½å¯ç±çå¼è¡¨æ¨åºï¼æè 亦å¯ç´æ¥ååºçå¼è¡¨ä»£æ¿æ¤ç¨åº
signal:x,y:std_logic;
begin
x<=a xor b;
y<=x and ci;
s<=x xor ci;
co<=y or (a and b);
end func;
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library ieee;
use ieee.std_logic_.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; --æ¤å å«æç±»å转æ¢å½æ°
entity bit2adder is
port(
a,b:in std_logic_vector(1 downto 0);
ci:in std_logic;
co:out std_logic;
s:out std_logic_vector(1 downto 0)
);
end bit2adder;
architecture func of bit2adder is
begin
process(a,b,ci) --æ´å¤ä½çä¹å¯æç §æ¤æè·¯æ¥å
variable temp:std_logic_vector(2 downto 0);
variable x,y,sum:ingeter;
begin
x:=conv_integer(a);
y:=conv_integer(b);
sum:=(x+y)+conv_integer(ci);
temp:=conv_std_logic_vector(sum,3);
s<=temp(1 downto 0);
co<=temp(2);
end process;
end func;